Commit ea75cdffe1b8902bf02b4c44efb405bfb92b3e4f

Authored by Loic Dachary
2 parents c431e1ff 7c2fcc5b
Exists in master

Merge branch 'wip-18092' into 'master'

gf_cpu.c: fix pclmul detection and add portable cpuid feature bit defs

See merge request !20
Showing 1 changed file with 17 additions and 5 deletions   Show diff stats
src/gf_cpu.c
... ... @@ -22,6 +22,18 @@ int gf_cpu_supports_arm_neon = 0;
22 22  
23 23 #if defined(__x86_64__)
24 24  
  25 +/* CPUID Feature Bits */
  26 +
  27 +/* ECX */
  28 +#define GF_CPU_SSE3 (1 << 0)
  29 +#define GF_CPU_PCLMUL (1 << 1)
  30 +#define GF_CPU_SSSE3 (1 << 9)
  31 +#define GF_CPU_SSE41 (1 << 19)
  32 +#define GF_CPU_SSE42 (1 << 20)
  33 +
  34 +/* EDX */
  35 +#define GF_CPU_SSE2 (1 << 26)
  36 +
25 37 #if defined(_MSC_VER)
26 38  
27 39 #define cpuid(info, x) __cpuidex(info, x, 0)
... ... @@ -50,7 +62,7 @@ void gf_cpu_identify(void)
50 62 cpuid(reg, 1);
51 63  
52 64 #if defined(INTEL_SSE4_PCLMUL)
53   - if ((reg[2] & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE4_PCLMUL")) {
  65 + if ((reg[2] & GF_CPU_PCLMUL) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE4_PCLMUL")) {
54 66 gf_cpu_supports_intel_pclmul = 1;
55 67 #ifdef DEBUG_CPU_DETECTION
56 68 printf("#gf_cpu_supports_intel_pclmul\n");
... ... @@ -59,7 +71,7 @@ void gf_cpu_identify(void)
59 71 #endif
60 72  
61 73 #if defined(INTEL_SSE4)
62   - if (((reg[2] & (1<<20)) != 0 || (reg[2] & (1<<19)) != 0) && !getenv("GF_COMPLETE_DISABLE_SSE4")) {
  74 + if (((reg[2] & GF_CPU_SSE42) != 0 || (reg[2] & GF_CPU_SSE41) != 0) && !getenv("GF_COMPLETE_DISABLE_SSE4")) {
63 75 gf_cpu_supports_intel_sse4 = 1;
64 76 #ifdef DEBUG_CPU_DETECTION
65 77 printf("#gf_cpu_supports_intel_sse4\n");
... ... @@ -68,7 +80,7 @@ void gf_cpu_identify(void)
68 80 #endif
69 81  
70 82 #if defined(INTEL_SSSE3)
71   - if ((reg[2] & (1<<9)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSSE3")) {
  83 + if ((reg[2] & GF_CPU_SSSE3) != 0 && !getenv("GF_COMPLETE_DISABLE_SSSE3")) {
72 84 gf_cpu_supports_intel_ssse3 = 1;
73 85 #ifdef DEBUG_CPU_DETECTION
74 86 printf("#gf_cpu_supports_intel_ssse3\n");
... ... @@ -77,7 +89,7 @@ void gf_cpu_identify(void)
77 89 #endif
78 90  
79 91 #if defined(INTEL_SSE3)
80   - if ((reg[2] & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE3")) {
  92 + if ((reg[2] & GF_CPU_SSE3) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE3")) {
81 93 gf_cpu_supports_intel_sse3 = 1;
82 94 #ifdef DEBUG_CPU_DETECTION
83 95 printf("#gf_cpu_supports_intel_sse3\n");
... ... @@ -86,7 +98,7 @@ void gf_cpu_identify(void)
86 98 #endif
87 99  
88 100 #if defined(INTEL_SSE2)
89   - if ((reg[3] & (1<<26)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE2")) {
  101 + if ((reg[3] & GF_CPU_SSE2) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE2")) {
90 102 gf_cpu_supports_intel_sse2 = 1;
91 103 #ifdef DEBUG_CPU_DETECTION
92 104 printf("#gf_cpu_supports_intel_sse2\n");
... ...