Commit 9afc35f3a1c48f9486e6cf0afa39ea66c4e9e37f

Authored by dx9
1 parent c431e1ff

gf_cpu.c: fix pclmul detection and use gcc/clang provided bit defs

Fixes: http://tracker.ceph.com/issues/18092

Signed-off-by: John Coyle <dx9err@gmail.com>
Showing 1 changed file with 5 additions and 5 deletions   Show diff stats
src/gf_cpu.c
... ... @@ -50,7 +50,7 @@ void gf_cpu_identify(void)
50 50 cpuid(reg, 1);
51 51  
52 52 #if defined(INTEL_SSE4_PCLMUL)
53   - if ((reg[2] & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE4_PCLMUL")) {
  53 + if ((reg[2] & bit_PCLMUL) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE4_PCLMUL")) {
1
  • Loic avatar small 75dpi
    Loic Dachary @dachary (Edited )

    It was incorrectly set to

    #define bit_SSE3 (1 << 0)

    it should have been

    #define bit_PCLMUL (1 << 1)

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54 54 gf_cpu_supports_intel_pclmul = 1;
55 55 #ifdef DEBUG_CPU_DETECTION
56 56 printf("#gf_cpu_supports_intel_pclmul\n");
... ... @@ -59,7 +59,7 @@ void gf_cpu_identify(void)
59 59 #endif
60 60  
61 61 #if defined(INTEL_SSE4)
62   - if (((reg[2] & (1<<20)) != 0 || (reg[2] & (1<<19)) != 0) && !getenv("GF_COMPLETE_DISABLE_SSE4")) {
  62 + if (((reg[2] & bit_SSE4_2) != 0 || (reg[2] & bit_SSE4_1) != 0) && !getenv("GF_COMPLETE_DISABLE_SSE4")) {
1
  • Loic avatar small 75dpi
    Loic Dachary @dachary (Edited )
    #define bit_SSE4_2  (1 << 20)
    #define bit_SSE4_1  (1 << 19)
    
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63 63 gf_cpu_supports_intel_sse4 = 1;
64 64 #ifdef DEBUG_CPU_DETECTION
65 65 printf("#gf_cpu_supports_intel_sse4\n");
... ... @@ -68,7 +68,7 @@ void gf_cpu_identify(void)
68 68 #endif
69 69  
70 70 #if defined(INTEL_SSSE3)
71   - if ((reg[2] & (1<<9)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSSE3")) {
  71 + if ((reg[2] & bit_SSSE3) != 0 && !getenv("GF_COMPLETE_DISABLE_SSSE3")) {
1
72 72 gf_cpu_supports_intel_ssse3 = 1;
73 73 #ifdef DEBUG_CPU_DETECTION
74 74 printf("#gf_cpu_supports_intel_ssse3\n");
... ... @@ -77,7 +77,7 @@ void gf_cpu_identify(void)
77 77 #endif
78 78  
79 79 #if defined(INTEL_SSE3)
80   - if ((reg[2] & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE3")) {
  80 + if ((reg[2] & bit_SSE3) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE3")) {
1
81 81 gf_cpu_supports_intel_sse3 = 1;
82 82 #ifdef DEBUG_CPU_DETECTION
83 83 printf("#gf_cpu_supports_intel_sse3\n");
... ... @@ -86,7 +86,7 @@ void gf_cpu_identify(void)
86 86 #endif
87 87  
88 88 #if defined(INTEL_SSE2)
89   - if ((reg[3] & (1<<26)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE2")) {
  89 + if ((reg[3] & bit_SSE2) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE2")) {
1
90 90 gf_cpu_supports_intel_sse2 = 1;
91 91 #ifdef DEBUG_CPU_DETECTION
92 92 printf("#gf_cpu_supports_intel_sse2\n");
... ...